Optimizing DRAM Throughput on Apple M3 Neural Engine via Kernel DMA Adjustments

An RTL performance erratum in Apple's M3 Neural Engine was resolved by optimizing kernel DMA engine prefetch ring behavior, restoring DRAM weight streaming throughput to 50 GB/s. This improvement significantly boosted Llama 3.2 1B and Qwen3-8B model performance metrics.

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